1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device in which a defective memory cell if any is replaced by a normal one.
2. Description of the Background Art
In a mass storage semiconductor device such as a dynamic random access memory (DRAM), a very small portion of a memory circuit fails to work normally due to the dust particles attached to a memory cell during wafer process fabrication.
Then, a common practice to fabricate a chip in which every memory cell operates normally is to preliminarily form spare memory cells as substitute for defective cells.
More specifically, conventionally, every memory circuit has been tested after wafer processing, and based on the results, a fuse circuit on a chip has been disconnected by a laser to replace a defective portion by a redundancy circuit.
FIG. 14 is a circuit diagram showing a conventional redundancy circuit. As shown in FIG. 14, the redundancy circuit includes a node N1 for outputting a signal to activate a redundancy word line and inactivate a normal word line, a plurality of fuses 1 connected to the node N1, and a plurality of N channel MOS transistors NT1 respectively connected between fuse 1 and a ground node.
FIG. 15 is a diagram showing a structure of a conventional 7 bit (128 value) decoder circuit. As shown in FIG. 15, the decoder circuit includes a plurality of AND circuits 3 connected to respective word lines WL and shunt lines, a plurality of decoder lines (first layer aluminum interconnections) 5, which are connected three by three to each AND circuit 3, and a plurality of second layer aluminum interconnections 7 arranged to intersect decoder lines 5. Decoder lines 5 and second layer aluminum interconnections 7 are connected by via holes 9.
In FIGS. 14 and 15, selection signals of XJ, XK and XL groups are those decoded by 2, 2 and 3 bit addresses, respectively. As shown in FIG. 15, each AND circuit 3 is connected to one of the second layer aluminum interconnections 7 from each of XJ, XK and XL groups, respectively, and one of 128 word lines WL is selected. At this time, if one of the 128 word lines WL is connected to a defective memory cell, this single word line can be substituted with a redundancy word line. This substitution is accomplished by disconnecting one of fuses 1 of each of XJ, XK and XL groups. This allows the potential of node N1, which was precharged to a high level by turning on a P channel MOS transistor PT1 before the selection of a specific memory cell by an address, to be retained at a high level even after the selection by the address, so that a high level signal for activating a redundancy word line and inactivating a defective word line can be output from node N1.
Such a redundancy circuit is provided to repair any defective portion accidentally resulting at an unspecific address during chip fabrication, and a photomask, used in fine patterning of memory cells, has been required to be totally free from defects, that is, perfect.
However, the recent scaling down and increasing of capacity for semiconductor memory devices are making manufacture of perfect photomasks more and more difficult. More specifically, a Levenson phase shift mask, which is highly useful for transferring fine patterns in particular, requires a shifter which partially inverts the phase of a light by 180.degree., in addition to optically transparent and non-transparent portions. The modification of the shifter, however, is very difficult, thereby making manufacture of the perfect photomasks unpromising.
On the other hand, since fabrication of chips with a defective photomask makes the same portion of memory circuits always defective, a conventional method requires that the same portion of every chip should always be substituted with a redundancy circuit, resulting in a problem of decreased productivity due to the time required for the circuit disconnection.
Another problem was that a number of redundancy circuits required to allow a number of defects to be repaired resulted in increased chip area, because of need of the large fuse circuit area.